{"id":2368,"date":"2023-08-09T00:35:38","date_gmt":"2023-08-08T19:05:38","guid":{"rendered":"http:\/\/sites.iitgn.ac.in\/digitalstudies\/?page_id=2368"},"modified":"2023-08-09T00:36:21","modified_gmt":"2023-08-08T19:06:21","slug":"photo-post-aryan","status":"publish","type":"page","link":"http:\/\/sites.iitgn.ac.in\/digitalstudies\/photo-post-aryan\/","title":{"rendered":"Photo Post – Aryan"},"content":{"rendered":"

The Circuitry of Life: My Journey at the NanoDC Lab<\/strong><\/p>\n

Greetings! Today, I would like to share with you my experience at the NanoDC lab. First, let me give you\u00a0a brief introduction to the lab. The NanoDC lab is a highly competitive research lab located in Academic\u00a0Block 5(5\/207) at IITGN. It is co-owned by four esteemed professors: Prof Nihar Ranjan Mohapatra, Prof\u00a0Joycee Mekie, Prof Tarun Agarwal, and Prof Jhuma Saha. The lab conducts research on a broad spectrum\u00a0of topics ranging from Semiconductor Devices to Circuits to Architectures. Now, let’s delve into my\u00a0journey at the NanoDC lab.<\/p>\n

From childhood, I was never actively involved in technology. The only reason I cleared JEE and came into IIT was my love for math and physics. Since I am from the 2020 batch, our first three semesters\u00a0happened online. Since I am an introvert, I didn\u2019t interact much with my seniors and batch mates. Due to\u00a0this, I didn\u2019t explore coding, ML or other interesting subjects partially due to my lack of interest and\u00a0because of the fact that I thought that what’s taught in the lectures would be enough for me. Time passed\u00a0on and our first year went by. In the third semester, I took a course \u201cDigital Systems\u201d offered by Prof\u00a0Joycee Mekie.This course was literally the turning point in my life at IITGN. The course covers basic\u00a0concepts of hardware and digital processors. I fell in love with the course particularly because of the way\u00a0Prof Joycee Mekie taught us. I scored the highest marks in this course. Still after the course, I hadn\u2019t\u00a0decided what I wanted to do in my life. Then the fourth semester happened and I came to college. It was\u00a0the first offline semester and the first semester where I had to choose an additional course. I was confused\u00a0since I didn\u2019t really know at that point of time what my interests were. I decided to take a project under\u00a0Prof Joycee Mekie. It was regarding Hardware Accelerators for ML Applications. However, I was the\u00a0only student taking this project and because of lack of confidence in my abilities that I won’t be able to\u00a0complete the project, I dropped it and instead took Computer Architecture and Organization. Fourth\u00a0semester passed and now it was the time for a 2nd year summer internship. Still, I was clueless about my\u00a0academic interests. I decided that I would do extensive coding that summer to prepare myself for the 3rd\u00a0summer intern interviews. One fine day, I saw a poster on a notice board in the Academic Area where\u00a0there was an advertisement regarding the SRIP(Summer Research Internship Program) offered at IITGN.\u00a0I decided to apply for it since they were giving a stipend of 16K per month. Fortunately, I got selected\u00a0into it and my project was the same project which I didn\u2019t take last semester, Hardware accelerators under\u00a0Professor Joycee. But this time, I was determined to see it through.<\/p>\n

Over the summer, I engaged in reading diverse research papers, brainstorming innovative concepts, collaborating with fellow lab members, and developed an interest in a subject beyond the scope of my\u00a0academic coursework.<\/p>\n

During my internship, I worked with Cadence Genus, a software application used to synthesize RTL\u00a0designs into a standard cell based netlist provided by foundry, such as UMC 65nm, to calculate the\u00a0hardware’s frequency, area, power consumption, and check for timing violations. At the time, I was not\u00a0familiar with the tool’s operation as I mostly ran the provided tcl script for our verilog modules.<\/p>\n

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\nFigure 1. Tcl script used to run Genus<\/strong><\/p>\n

Nonetheless, the internship was an enriching experience that resulted in my publication of a research\u00a0paper at a prominent VLSI conference, ASP-DAC, during my second year of study.The internship\u00a0experience helped me realize my passion for pursuing a career in VLSI. In my fifth semester, I had 25\u00a0required credits, but as I had decided to pursue a career in semiconductors, I was eager to take a six-level\u00a0course on VLSI Design offered by Prof. Joycee. Despite the maximum number of credits per semester\u00a0being 28, I managed to convince my FA to allow me to take 29 credits. This led to a hectic yet rewarding\u00a0semester, where I was introduced to various tools used in the lab, including my personal favorite,\u00a0Cadence Virtuoso.<\/p>\n

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\nFigure 2. UI of Cadence Virtuoso<\/strong><\/p>\n

The Cadence Virtuoso is a versatile tool that enables the creation of circuits from scratch at a transistor\u00a0level, layout designs for these circuits, and simulation of pre-layout and post-layout for all pvt corners.\u00a0During the VLSI Design course, I extensively studied this tool as it is widely used in the lab. For the\u00a0course project, I opted for an SRAM PUF design, which required testing the reliability, uniqueness, and\u00a0randomness of the PUF. To do this, I utilized a script commonly employed in our lab to verify whether a\u00a0given PUF satisfies all NIST tests. This script is widely used in the lab to evaluate PUF performance. At\u00a0the end of the fifth semester, I became an expert in using Virtuoso.<\/p>\n

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\nFigure 3. PUF Script used to evaluate the performance of PUF<\/strong><\/p>\n

Presently, in my sixth semester, I am enrolled in a course called IC Design Laboratory, which involves\u00a0coding hardware in System Verilog. Throughout this course, I am utilizing three distinct tools, namely\u00a0Vivado, Genus, and NCSim. Vivado is primarily used to implement the hardware on an FPGA, and I\u00a0have utilized it in numerous assignments and in my current project, where I am implementing a RISC-V
\nprocessor.<\/p>\n

\"\"<\/a>
\nFigure 4. Start UI of Xilinx Vivado<\/strong><\/p>\n

During the IC Design Laboratory course, I received formal instruction on how to use Genus and gained a\u00a0better understanding of how to write tcl scripts. In addition to Genus and Vivado, I was introduced to\u00a0NCSim, a tool primarily utilized for post-synthesis and post-layout simulations in the ASIC flow. Thus\u00a0far, I am only familiar with these particular tools of the lab, but I am keen to explore other tools such as
\nInnovus and Tempus in the future.<\/p>\n

\"\"<\/a>
\nFigure 5. NCSim Software<\/strong><\/p>\n

In conclusion, my experience at the NanoDC lab has been truly enlightening and has played a crucial role\u00a0in shaping my understanding of the semiconductor industry. The lab has provided me with a platform to\u00a0gain hands-on experience with state-of-the-art tools such as Cadence Virtuoso, Genus, Vivado, and\u00a0NCSim, which are widely utilized in the industry. The research projects that I have undertaken have given\u00a0me a deeper understanding of various aspects of semiconductor design and have helped me develop\u00a0critical skills that are essential for success in this field. Furthermore, the support and guidance provided\u00a0by the lab’s faculty members especially by Kailash Prasad, Yaswanth Ram and Alok Pradhan have been\u00a0instrumental in my growth and development. The lab is home to some of the most accomplished\u00a0professors in the field of semiconductors, and their expertise has been invaluable in my journey so far.\u00a0Overall, I am immensely grateful for the opportunity to be a part of the NanoDC lab and look forward to\u00a0continued learning and growth in the year to come.<\/p>\n

Some Projects Completed Using These Tools<\/strong><\/p>\n

\"\"<\/a><\/p>\n

Figure 6. Schematic of a 6T SRAM Bit Cell<\/strong><\/p>\n

\"\"<\/a>
\nFigure 7. RTL Schematic of RISC-V Generated using Vivado<\/strong><\/p>\n

\"\"<\/a><\/p>\n

Figure 8. Python Script to Automate the process of Genus Synthesis<\/strong><\/p>\n

Other Miscellaneous Places of the Lab<\/strong><\/p>\n

\"\"<\/a><\/p>\n

Figure 9. A Wall of NanoDC Lab with research posters<\/strong><\/p>\n

At the NanoDC lab, there is a wall covered with research posters, displaying the latest work and findings\u00a0of the lab members. Every time I enter the lab, this wall catches my attention and inspires me to dive\u00a0deeper into the world of research. The posters, with their colorful illustrations and intriguing titles, make\u00a0me curious and motivated to learn more about the specific research areas. Looking at these posters, I
\nrealize the immense amount of work and dedication that goes into conducting research. It reminds me of\u00a0the endless possibilities and opportunities that await us in the field of semiconductor research. The posters\u00a0showcase a diverse range of topics, including novel device designs, circuit architectures, and verification\u00a0techniques. They also demonstrate the interdisciplinary nature of research, as many posters involve\u00a0collaborations with researchers from different fields.The wall of research posters at the NanoDC lab\u00a0serves as a reminder to me that research is a continuous and evolving process. It encourages me to keep\u00a0pushing my limits and exploring new areas of interest. Whenever I feel stuck or overwhelmed with a\u00a0particular project, I take a moment to stand in front of this wall and gain some inspiration from the
\nremarkable work displayed.<\/p>\n

\"\"<\/a>
\nFigure 10. Discussion wall at NanoDC Lab<\/strong><\/p>\n

At the NanoDC lab, there is a unique wall where people often gather to have discussions and brainstorm\u00a0ideas. This wall is adorned with beautiful illustrations and artwork that serve to inspire and stimulate\u00a0creativity. The artwork is a combination of various colors, shapes, and patterns, making it a visually\u00a0appealing space that stands out from the rest of the lab.What I find most fascinating about this wall is that\u00a0it serves as a physical representation of the creative and collaborative culture that is fostered within the\u00a0lab. It is a place where people come together to share their thoughts and ideas, and the illustrations on the\u00a0\u00a0wall serve to inspire and spark new ideas. Personally, I find this wall to be a source of inspiration and\u00a0motivation. Whenever I am stuck in my work or need a break, I often find myself drawn to this wall. I\u00a0spend some time admiring the artwork, which helps me to clear my mind and gain a fresh perspective.\u00a0The conversations and discussions that take place in front of this wall are always insightful and\u00a0thought-provoking, and I feel fortunate to be a part of such a vibrant and collaborative community.<\/p>\n

\"\"<\/a><\/p>\n

Figure 11. CPU desk at the lab<\/strong><\/p>\n

One of the most fascinating areas in the NanoDC lab is the desk where all the CPUs of the lab are kept.\u00a0 It’s a great sight to see so many different processors in one place. However, one particular CPU always catches my attention. It has an RGB display that changes colors every few seconds, making it a visually\u00a0captivating device. Whenever I pass by the desk, I can’t help but glance at it and appreciate its unique\u00a0design. It’s a reminder of how much innovation and creativity goes into the design of modern CPUs, and it motivates me to keep learning more about this field.<\/p>\n","protected":false},"excerpt":{"rendered":"

The Circuitry of Life: My Journey at the NanoDC Lab Greetings! Today, I would like to share with you my experience at the NanoDC lab. First, let me give you\u00a0a brief introduction to the lab. The NanoDC lab is a highly competitive research lab located […]<\/p>\n","protected":false},"author":4,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-2368","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"http:\/\/sites.iitgn.ac.in\/digitalstudies\/wp-json\/wp\/v2\/pages\/2368"}],"collection":[{"href":"http:\/\/sites.iitgn.ac.in\/digitalstudies\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"http:\/\/sites.iitgn.ac.in\/digitalstudies\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"http:\/\/sites.iitgn.ac.in\/digitalstudies\/wp-json\/wp\/v2\/users\/4"}],"replies":[{"embeddable":true,"href":"http:\/\/sites.iitgn.ac.in\/digitalstudies\/wp-json\/wp\/v2\/comments?post=2368"}],"version-history":[{"count":2,"href":"http:\/\/sites.iitgn.ac.in\/digitalstudies\/wp-json\/wp\/v2\/pages\/2368\/revisions"}],"predecessor-version":[{"id":2381,"href":"http:\/\/sites.iitgn.ac.in\/digitalstudies\/wp-json\/wp\/v2\/pages\/2368\/revisions\/2381"}],"wp:attachment":[{"href":"http:\/\/sites.iitgn.ac.in\/digitalstudies\/wp-json\/wp\/v2\/media?parent=2368"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}